The present invention relates to delay lines for digital systems. More specifically, the present invention relates to a tuneable and glitchless delay line.
Delay lines are used in digital circuits such as board level systems and integrated circuit (IC) devices, including field programmable gate arrays (FPGAs) and microprocessors, to control the timing of various signals in the digital circuits. A simple delay line receives an input signal on an input terminal and provides an output signal on an output terminal, the output signal being a copy of the input signal delayed by a certain time period that is referred to as the delay D of the delay line. More complicated delay lines are tuneable so that delay D of the delay line can be adjusted.
An IC device such as an FPGA can use a tuneable delay line to synchronize clock signals in various parts of the FPGA. As shown in FIG. 1, a circuit board 100 comprises an FPGA 105 and another IC device 150. FPGA 105 comprises a delay line 110 and configurable logic circuits 130. Clock signal CLK1 is coupled to an input terminal of delay line 110 and to the clocked circuits (not shown) of IC device 150. Delay line 110 drives a clock signal CLK2 to configurable logic circuits 130. Before clock signal CLK2 reaches configurable logic circuits 130, clock signal CLK2 may be skewed by various factors such as capacitance, heavy loading on the clock line, and propagation delay. The various skewing factors are represented by clock skew 140 which causes a skew delay on clock signal CLK2. To distinguish clock signal CLK2 from the skewed version of clock signal CLK2, the skewed version is referred to as skewed clock signal S_SLK2. Skewed clock signal S_SLK2 drives the clock input terminals (not shown) of the clocked circuits within configurable logic circuits 130. For proper operation of FPGA 105 with IC device 150, clock signal CLK1 should be synchronized with skewed clock signal S_SLK2. Clock signal CLK1 can be synchronized with skewed clock signal S_CLK2 by adjusting delay line 110 so that delay D plus skew delay S_D is equal to a multiple of the period of clock signal CLK1. Various circuits and methods of using delay lines to synchronize clock signals are well known in the art.
FIG. 2 shows a block diagram of a conventional tuneable delay line 200. Tuneable delay line 200 comprises a multi-tap delay circuit 210 and a multiplexer 220. Multi-tap delay circuit 210 is configured to receive an input signal IN and provide a plurality of delayed output signals D_O[0] to D_O[N] (also called taps). Each output signal is a copy of input signal IN delayed by some multiple of a basic delay of tuneable delay line 210. Specifically, delayed output signal D_O[0] is a copy of input signal IN delayed by zero times the basic delay, (i.e. not delayed). Delayed output signal D_O[1] is a copy of input signal IN delayed by the basic delay. Delay output signal D_O[2] is a copy of input signal IN delayed by two times the basic delay. In general, delayed output signal D_O[X] is a copy of input signal IN delayed by X times the basic delay. Some multi-tap delay circuits 210 may not provide delayed output signal D_O[0].
Multiplexer 220 is configured to receive some or all of the delayed output signals. Thus, the input terminals of multiplexer 220 are coupled to the output terminals of multi-tap delay circuit 210. To avoid confusion, terminals are referred to with the same identifier as the signals driven by the terminal. For example, delayed output signal D_O[2] is driven by output terminal D_O[2]. Multiplexer 220 is controlled by tap select signals TS[0-M]. As used herein, signals that logically form groups are referred to using a group name followed by brackets enclosing a number for each signal. If more than one signal is referred to simultaneously, brackets containing a range of numbers are used. For example tap select signals TS[0xe2x88x92M] comprise M+1 signals TS[0], TS[1], TS[2]. . . TS[Mxe2x88x921], and TS[M]. Tap select lines TS[0-M] select which delayed output signal multiplexer 220 drives output terminal OUT.
FIG. 3A is a block diagram that illustrates multi-tap delay circuit 210 in more detail. The delay circuit of FIG. 3A comprises a plurality of delay elements 310_0 to 310_Nxe2x88x921. Delay elements 310_1 to 310_Nxe2x88x921 are coupled in series so that the input terminal of a delay element 310_X is coupled to the output terminal of a delay element 310_Xxe2x88x921, where X is an integer from 1 to Nxe2x88x921. The input terminal of delay element 310_0 is coupled to input terminal IN of multi-tap delay circuit 210. Each delay element 310_X drives a delayed output signal D_O[X+1]. Delayed output signal D_O[0] is provided at the input terminal of delay element 310_0. Typically, each delay element is identical and provides a delay equal to the base delay. Thus, each delayed output signal D_O[X] is delayed by the base delay from the previous delayed output signal D_O[Xxe2x88x921].
FIG. 3B shows a typical delay element 350. Delay element 350 comprises an inverter 351 coupled in series with an inverter 352. Logically, inverter 351 and inverter 352 cancel out. However, both inverter 351 and inverter 352 provide a small propagation delay. Thus, for delay element 350 the base delay is equal to the propagation delay of inverter 351 plus the propagation delay of inverter 352. Other types of delay elements are also well known in the art and can be used in multi-tap delay circuits.
As explained above, multiplexer 220 (FIG. 2) selects a delayed output signal from multi-tap delay circuit 210 to drive output terminal OUT. However, conventional multiplexers sometimes produce glitches due to race conditions on select lines TS[0-M]. For example, FIG. 4 is a circuit diagram illustrating a version of multiplexer 220, where N=16. To switch from delayed output signal D_O[7] to delayed output signal D_O[8], tap select signals TS[0-3] must transition from 0111 (binary) to 1000 (binary). During the transition from 0111 to 1000, tap select signals TS[0-3] may transition temporarily to 1111, which would temporarily select delayed output signal D_O[15]. For example, if delayed output signal D_O[15] is at a logic high level while the desired delayed output signal D_O[8] is at a logic low level, a glitch appears on output signal OUT. If delay line 200 is being used for synchronizing clock signals as shown in FIG. 1, the temporary transition to the logic high level caused by the glitch may erroneously trigger clocked elements of configurable logic circuits 130, thereby causing FPGA 100 to perform erroneously. Hence, there is a need for a tuneable delay line that provides glitchless operation.
The invention provides a tuneable delay line that uses a unique Gray code multiplexer to select the appropriate delayed output signal without glitches by eliminating race conditions on the multiplexer select signals. The invention takes advantage of the fact that the delay line settings change in an ordered fashion, i.e., the settings are sequentially ordered. Specifically, in one embodiment of the present invention a delay line comprises a multi-tap delay circuit that generates a plurality of sequentially ordered delayed output signals on a plurality of sequentially ordered delayed output terminals. The input terminals of a Gray code multiplexer are coupled to the sequentially ordered output terminals of the multi-tap delay circuit. The Gray code multiplexer routes one of the delayed output signals to an output terminal in response to a Gray code value applied to the Gray code control terminals of the Gray code multiplexer.
The delay provided by the delay line is adjusted by increasing or decreasing the Gray code value applied to the Gray code control terminals of the Gray code multiplexer. Specifically, to increase the delay provided by the delay line by one base delay, the Gray code value applied to the Gray code control terminals of the Gray code multiplexer is increased by one. Conversely, to decrease the delay provided by the delay line by one base delay, the Gray code value applied to the Gray code control terminals of the Gray code multiplexer is decreased by one.
One embodiment of the Gray code multiplexer is implemented using a multiplexer tree having a first level and a last level. The last level is a first multiplexer having a first input terminal and a second input terminal. The first level of the multiplexer tree includes a second multiplexer and a third multiplexer. The second multiplexer has an output terminal coupled to the first input terminal of the first multiplexer, and a plurality of sequentially ordered input terminals coupled to a first subset of the sequentially ordered delayed output terminals of the multi-tap delay circuit. The third multiplexer has an output terminal coupled to the second input terminal of the first multiplexer, and a plurality of sequentially ordered input terminals reversedly coupled to a second subset of sequentially ordered delayed output terminals of the multi-tap delay circuit. The reverse coupling of the sequentially ordered input terminals of the third multiplexer allows the Gray code to be implemented, since adjacent settings have addresses that differ by only one bit.
The present invention will be more fully understood in view of the following description and drawings.